1. Field of the Invention
The present invention relates to input/output (I/O) circuits and electrostatic discharge (ESD) protection circuits, and in particular, to I/O circuits and ESD protection circuits that have a reduced layout area and which experience improved ESD performance.
2. Description of the Prior Art
An NMOSFET is a very effective ESD protection device. In one known application, with the gate connected to a gate-driving signal, the NMOSFET is used as the pull-down device of a CMOS buffer to drive an output voltage. In another known application, with the gate electrically connected to ground, the NMOSFET is used to protect an input pin or power bus during an ESD event.
In a PS mode (i.e., power to Vss) ESD event, when a positive ESD transient voltage is applied to an IC pin while a VSS power pin is at ground potential, the protection of an NMOSFET depends greatly on the snap-back mechanism for conducting large amounts of ESD current between the drain and source. To start, the high electric field at the drain junction causes impact ionization, which generates both minority and majority carriers. The minority carriers flow toward the drain contact and the majority carriers flow toward the substrate/Pwell contact to cause a local potential build up in the current path in the Pwell. When the local substrate potential is 0.6V higher than the adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction injects minority carriers (electrons) into the Pwell, and these minority carriers eventually reach the drain junction to further enhance the impact ionization. As a continuous loop, the MOSFET gets into a low impedance (snap back) state to conduct large amounts of ESD current.
In a multi-finger NMOS structure as shown in FIGS. 1a and 1b, not all gate fingers may turn on during an ESD event. This is because the first few gate fingers, having turned on quickly, get into a snap-back low-impedance condition, thereby reducing the drain terminal to source terminal voltage to a transient voltage which is less than the trigger voltage of the NMOS device. This potentially prevents other gate fingers from turning on. Therefore, with only a limited number of gate fingers turned on to absorb the ESD energy, the size of the NMOSFET is effectively reduced and the ESD performance degrades.
When a gate finger is triggered in an ESD event, the entire finger turns on. This is due to a cascading effect that a local source junction in a forward biasing state will inject lots of carriers into the substrate to flow towards the drain junction, which in turn generates more minority carriers (due to impact ionization) flowing back towards the p+ guard ring to raise the adjacent Pwell potential. Therefore, the adjacent source region is also turned into a forward bias state. With this cascading effect, the entire gate finger turns on into a snap back condition.
Experimental data has shown that a medium-to-long gate-finger NMOS structure (e.g., 40 um×2 or 100 um×2 fingers) as shown in FIG. 2 has a better PS-mode ESD performance than a short-gate-finger structure (e.g., 20 um×10 fingers) as shown in FIG. 1a, despite the fact that both structures have the same total gate width of 200 um. This is because each finger in a short-gate-finger structure represents only a small percentage of the total gate width, and during a PS-mode ESD event, only a few fingers will be turned on for the reasons described above in connection with FIGS. 1a and 1b. 
Prior art MOSFET-based I/O structures with self-ESD protection typically include a number of NMOSFET and PMOSFET transistors. As shown in FIGS. 3a and 3b, the pull-down NMOSFET may comprise a number of gate elements, with some gate elements connected to a first gate signal for the output transistor portion, and some gate elements connected to the VSS bus/Ground as the input protection ESD structure. Similarly, the pull-up PMOSFET may comprise a number of gate elements, with some gate elements connected to a second gate signal for the output transistor portion, and some gate elements connected to the VDD bus as the input protection ESD structure. In the prior art, a gate element formed of a polysilicon element is typically coupled either to a gate signal or to a power bus.
FIG. 4 shows a typical layout of a conventional I/O cell or input ESD protection circuit having pull-up PMOS and pull-down NMOS multi-gate-finger transistors coupled to an IC pad. When used as an input ESD protection circuit, the PMOS gate is coupled to the VDD bus and the NMOS gate is coupled to the VSS bus. When used as an output circuit, the PMOS gate and NMOS gate are coupled to the same or different gate signals. The PMOS gate is node A, while the NMOS gate is node B. Node A can be connected to the VDD bus, while node B can be connected to the VSS bus for input protection. Alternatively, nodes A and B can be connected to an input signal such that the NMOS and the PMOS function as a CMOS-inverter output buffer. As yet another alternative, nodes A and B can be coupled to different signals for a flexible control of the state of the NMOS and the PMOS.
In the layout of FIG. 4, the NMOS gate fingers 20 and PMOS gate fingers 22 are disposed parallel to each other, and can be positioned on the same side of a bond pad 24. Alternatively, these fingers 20, 22 can be positioned on the opposite sides (not shown) of a bond pad 24. In addition, each NMOS gate finger 20 is generally aligned with a corresponding PMOS gate finger 22, and the pitch p (as defined below) between the source contact and the drain contact for each gate finger 20, 22 is also approximately the same. In addition, FIG. 4 also shows that the channel width CWN of each gate finger 20 in the NMOS is about the same as the channel width CWP of each gate finger 22 in the PMOS. In this regard, since a PMOS has lower mobility, when it is used as an output buffer, each PMOS gate finger 22 needs to be at least as long as, and maintain the same pitch as, each NMOS gate finger 20.
The following are some definitions for terms that will be used throughout this disclosure:
“Pitch” (denoted by “p”) means the distance between the center of the drain contact and the center of the source contact for each gate finger.
“DCGS” means drain-contact-to-gate-spacing.
“SCGS” means source-contact-to-gate-spacing.